Field of the Invention
The present invention relates to a display device, and more particularly, to a display device including a panel with a built-in gate driver and a method of driving the same.
Discussion of the Related Art
A flat panel display (FPD) device is applied to various electronic devices such as portable phones, tablet personal computers (PCs), notebook computers, monitors, etc. Examples of the FPD device include liquid crystal display (LCD) devices, plasma display panel (PDP) devices, organic light emitting display (OLED) devices, etc. Recently, electrophoretic display (EPD) devices are being widely used as one type of the FPD device.
As a type of FPD device (hereinafter referred simply to as a display device), organic light emitting display devices are self-emitting devices that self-emit light, and thus have a fast response time, high emission efficiency, high luminance, and a broad viewing angle.
A gate driver applied to an organic light emitting display device may be implemented as an integrated circuit (IC), and may be equipped in a panel configuring the organic light emitting display device. However, the gate driver may be directly provided in the panel in a gate-in panel (GIP) type.
Particularly, in a panel where thin film silicon formed of low temperature poly-silicon (LTPS) is formed, the gate driver using the GIP type outputs a scan pulse and various kinds of signals to the panel.
FIG. 1 is a waveform diagram showing a driving timing of a related art shift register, and FIG. 2 is a circuit diagram of the related art shift register.
The gate driver provided in the GIP type includes a shift register illustrated in FIG. 2. The shift register includes a plurality of stages, each of which may be configured as illustrated in FIG. 2. A signal Vout output from each of the stages is a scan signal transferred to a gate line which is formed in a panel.
The scan signal includes a scan pulse, having a turn-on voltage which turns on a switching element of each of a plurality of pixels connected to the gate line, and a turn-off signal for maintaining a turn-off state of the switching element during the remaining period of one frame.
Generally, each stage outputs the scan pulse once during one frame, and the scan pulse is sequentially output from the plurality of stages.
As illustrated in FIG. 2, each of the stages which sequentially output the scan pulse is turned on or off according to a logical state of a Q node. Each of the stages includes a pull-down transistor T6 and a pull-up transistor T7 which receive a fourth clock CLK4 to output the scan pulse when being turned on.
The pull-up transistor T7 is connected between the pull-down transistor T6 and a high-level voltage VGH terminal, and when the pull-down transistor T6 is turned on, the pull-up transistor T7 is turned off. When the pull-down transistor T6 is turned off, the pull-up transistor T7 is turned on, and outputs the turn-off signal.
For example, when the shift register operates by using four clocks CLK1 to CLK4, as shown in FIG. 1, the fourth clock CLK4 and a reset signal QRST are simultaneously input to the stage so as to reset the Q node and the shift register.
In this case, as illustrated in FIG. 3, the Q node may not normally be reset in an initial operation section of the shift register.
FIG. 3 is an exemplary diagram illustrating a state in which the Q node is not normally reset in an initial operation of the related art shift register, and FIG. 4 is an exemplary diagram illustrating a configuration of a stage which is included in the related art shift register and outputs an emission signal EM.
Referring to FIG. 3, a load of the reset signal QRST is greater than that of the fourth clock CLK4, and thus, a reset transistor Tqrst turned on by the reset signal QRST may be turned on late. In this case, short circuit can occur (OV output).
In this case, the Q node and a QB node are not simultaneously reset, and for this reason, the shift register cannot normally be driven.
Causes of the above-described problems are as follows.
A size of the reset transistor Tqrst driven by the reset signal QRST is generally smaller than that of the pull-down transistor T6. A load is greatly applied to the reset signal QRST depending on the number of the scan pulses (1,280 scan pulses with respect to high-definition (HD) resolution)
Therefore, as shown in FIG. 1, when the reset signal QRST and the fourth clock CLK4 are simultaneously input to the stage, the pull-down transistor T6 is turned on prior to the reset transistor Tqrst. The fourth clock CLK4 can be output to the gate line before the Q node is reset. In this case, the pull-up transistor T7 is turned on by the QB node in an unknown state, and for this reason, output short circuit can occur.
As illustrated in FIG. 4, the above-described abnormal operation of the organic light emitting display device using the GIP type can occur even in a stage which outputs the emission signal EM.
That is, in the related art organic light emitting display device, when the shift register initially operates, the above-described abnormal operation can occur. Particularly, the abnormal operation can severely occur in a shift register of an organic light emitting panel formed of a plastic substrate.
In an organic light emitting panel formed of a glass substrate, performance is not very good in terms of a reliability of a thin film transistor (TFT). Also, as a size and resolution of the organic light emitting panel increase, a load applied to the organic light emitting panel increases, and for this reason, a driving characteristic of the shift register is unstable.